Programming Logic

Prolog is the bane of my existence

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0 Replies - 1326 Views - Last Post: 03 December 2006 - 01:12 PM Rate Topic: -----

#1 William_Wilson  Icon User is offline

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Programming Logic

Posted 03 December 2006 - 01:12 PM

I don't know what you think, but prolog is probably the least logical coding language i've ever used. It makes less sense than Assembly, Scheme and a host of basic languages. The fact that error checking is almost impossible doesn't make me like it any more either.
With that out of the way.
My assignment is 7 long questions from a tic-tac-toe game, logic gates (connecting), graphs, etc... yes this is one assignment. After being out of commision with my knee for a couple weeks i'll admit i missed some lectures, but i've read the material and it does get near as complicated as he wants. Needless to say i'm running out of time to do the assignment and pissed off because i have to go to work, instead of finishing it, but here's my question anyway:

/*Gates*/
gate(a1,and).
gate(a2,and).
gate(a3,and).
gate(b1,or).
gate(b2,or).
gate(b3,or).
gate(c1,xor).
gate(c2,xor).
gate(c3,xor).

/*Gate Rules*/
and(1,1,B) :- B is 1,!.
and(0,1,B) :- B is 0,!.
and(1,0,B) :- B is 0.

or(1,_,B)  :- B is 1,!.
or(_,1,B)  :- B is 1,!.
or(0,0,B)  :- B is 0.

xor(1,0,B) :- B is 1,!.
xor(0,1,B) :- B is 1,!.
xor(X,X,B) :- B is 0. /*when 2 inputs match*/

wire(InputGate,OutputGate) :-
	gate(InputGate,T1),  /*InputGate must exist*/
	gate(OutputGate,T2), /*OutputGate must exist*/
	wire(T1,T2,T1).
	
wire(InGate,[H,T],OutGate,Output):-
	and(H,T,Output).



i realize i likely need another wire predicate, and that the first should not be passing T1,T2,T1, but i just needed something to see what is happening, and that it is the correct method.
We are supposed to be able to link gates together with outputs as inputs, implemented as a tree (i'm guessing).

How can i use T1 and T2 as the gate parameters they really are?

if i can get that working, linking shouldn't be too much of a problem.

InGate is the current gate,
H|T are the input values
Outgate is the gate getting the output value(if there is one)
Output is the value produced in this gate...
perhaps i'm going about this all wrong, because i'm used to top down code/O-O programming.
If you see anything i'm doing wrong, or even a suggestion on how wire/gate should work together, please post!

I just feel so stupid right now, i've never had such trouble with a coding language and had know way to tell if i'm doing it right.

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