[4thkyuubi]

I really do not know where to put this topic, since it is a pretty general question(had this project to write this code in C, I was doing the pipeline of the branch instruction)

Say if a computer with an ALU, containing the following operations,

ADD, SUB, DIV, MUL, SHL, SHR, NOT, OR, XOR AND

How can the ALU perform the conditional statement for the branch?
Say, let A be register1
And let B be register2
And let C be tempRegister

(A - B) --> C //perform ALU's SUB, and store result of A - B in C

The next part is where I am stuck, and I am stuck on how will the ALU perform this, as i can only use the provided operations above, I think?

If (C == 0) //if C is zero (A and B are equal)
//set program counter to the offset



Thanks in advance for anyone who took their time to read this!

This post has been edited by GunnerInc: 02 June 2012 - 01:11 PM
Reason for edit:: Disabled emoticons so code displays properly

[GunnerInc]

Moving to Assembly

[GunnerInc]

CPUs have a special register for conditions. The x86 has the EFLAGS register that gets set depending on a condition after an operation. The LC-2 has 3 condition codes N, Z, P which get set depending on the operation.

http://users.ece.ute...pacf88_appa.pdf

[turboscrew]

I think LC2200 might use BEQ $t1, $zero, label
Is the LC2200 this?
Or if that's not allowed, you really have a problem, because
there is no way directly accessing the PC.

[4thkyuubi]

Hello,

turboscrew, yes, that is the exact LC-2200 I am doing. I am not really sure if I understood this exercise. Right out of the book, it says



Show the actions in each stage of the pipeline for the BEQ instruction of the LC-2200.




Here is an example of each stage of the pipeline for the ADD instruction of the LC-2200.
IF Stage (cycle 1):

I-MEM[PC] -> FBUF //the instruction at memory address given by PC is fetched and placed in FBUF (which is essentially the IR)
PC + 1 -> PC //Increment PC



ID/RR stage (cycle 2):

DPRF[FBUF[Ry]]->DBUF[A] //read Ry into DBUF[A]
DPRF[FBUF[Rz]]->DBUF[B] //read Rz into DBUF[B]
FBUF[OPCODE]->DBUF[OPCODE] //copy opcode from FBUF to DBUF
FBUF[Rx]->DBUF[Rx] //copy Rx register specifier from FBUF to DBUF


EX stage (cycle 3):
DBUF[A]+DBUF[B]->EBUF[Result] //perform addition
DBUF[OPCODE]->DBUF[OPCODE] //copy opcode from DBUF to EBUF
DBUF[Rx]->EBUF[Rx] //copy Rx register specifier from DBUF to EBUF


MEM stage (cycle 4):
DBUF->FBUF //The MEM stage has nothing to contribute toward the execution of the ADD instruction, so simply copy the DBUF to MBUF

WB stage (cycle 5):
MBUF[Result]->DPRF[MBUF[RX]] //write back the result of the addition into the register specified by Rx

/////////////////////////////////////////////////////////////
I am trying to do a similar steps like this for the BEQ and I was stuck particularly at the EX stage, I was not really sure how to perform the if condition. My current approach is shown below:

IF Stage (cycle 1):
I-MEM[PC] -> FBUF //the instruction at memory address given by PC is fetched and placed in FBUF (which is essentially the IR)
PC + 1 -> PC //Increment PC


ID/RR stage (cycle 2):
DPRF[FBUF[Rx]]->DBUF[A] //read Rx into DBUF[A]
DPRF[FBUF[Ry]]->DBUF[B] //read Ry into DBUF[B]
FBUF[OPCODE]->DBUF[OPCODE] //copy opcode from FBUF to DBUF
FBUF[OFFSET]->DBUF[OFFSET] //not sure if this makes sense, but this is what I got intuitively based on the ADD’s EX stage in the pipeline.


EX stage (cycle 3):
DBUF[A] - DBUF[B] -> EBUF[Result] //perform subtraction
Here is where I am stuck, I am trying to check if EBUF[RESULT] == 0, and if it is, I increment the PC with the OFFSET.
DBUF[OPCODE]->DBUF[OPCODE] //copy opcode from DBUF to EBUF


MEM stage (cycle 4):
DBUF->FBUF //The MEM stage has nothing to contribute toward the execution of the ADD instruction, so simply copy the DBUF to MBUF


WB stage (cycle 5):
//not sure at this point

Also, id like to ask what is the purpose of the Z register for the ADD instruction? Why cant it work with just 2 operands compared to other machines?

[turboscrew]

All I know about the LC 2200 is what I found in the net, so that's not much. I wonder, though, if the internal actions are similar to MIPS'.

Is this of any help?

The 3-operand add (and many other instructions) is a RISC-fearure (RISC = Reduced Instruction Set Computer). It helps writing tighter code when the instruction doesn't mess up the source values (no need to reload original values, nor transferring the result with an additional instruction). Think of a compiler here.

This post has been edited by turboscrew: 05 June 2012 - 04:52 AM