[direwolf]

I am having trouble with the vhdl text for the j-k flip-flop. Below is the code I have created and the errors I am getting.


I am lost on troubleshooting this code. I have tried to figure out where I am wrong but everything looks like it should compile properly. I am using quartus II to copile and simulate. Any help would be appreciated, thanks in advance.

ENTITY jkff IS
 
PORT(
 
            J, K, P, R, CLK  :IN BIT;
 
            Q,QN                   :BUFFER BIT);
 
END jkff;
 
ARCHITECTURE circuit OF jkff IS
 
BEGIN
 
     PROCESS (CLK,P,R)
 
     BEGIN
 
            IF R = ‘0’ THEN
 
                 Q <= ‘0’; QN <= ‘1’;
 
            ELSIF P = ‘0’ THEN
 
                 Q <= ‘1’; QN <= ‘0’;
 
            ELSIF CLK’EVENT AND CLK = ‘0’ THEN
 
                 IF J = ‘0’ AND K = ‘0’ THEN           

Q <= Q; QN <= QN;
 
                 ELSIF J = ‘0’ AND K = ‘1’ THEN
 
                        Q <= ‘0’; QN <= ‘1’;
 
                 ELSIF J = ‘1’ AND K = ‘0’ THEN
 
                        Q <= ‘1’; QN <= ‘0’;
 
                 ELSIF J = ‘1’ AND K = ‘1’ THEN
 
                        Q <= QN; QN <= Q;
 
                 END IF;
 
            END IF;
 
     END PROCESS;
 
END circuit;

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Aug 04 08:08:30 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jkff -c jkff
Error (10500): VHDL syntax error at jkff.vhd(19) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(19) near text "‘"; expecting "(", or an identifier, or unary operator
Error (10500): VHDL syntax error at jkff.vhd(19) near text ’
Error (10500): VHDL syntax error at jkff.vhd(21) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(21) near text ’
Error (10500): VHDL syntax error at jkff.vhd(21) near text "‘"; expecting "(", or an identifier, or unary operator
Error (10500): VHDL syntax error at jkff.vhd(23) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(23) near text ’
Error (10500): VHDL syntax error at jkff.vhd(25) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(25) near text ’
Error (10500): VHDL syntax error at jkff.vhd(25) near text "‘"; expecting "(", or an identifier, or unary operator
Error (10500): VHDL syntax error at jkff.vhd(27) near text ’
Error (10500): VHDL syntax error at jkff.vhd(27) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(29) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(29) near text "‘"; expecting "(", or an identifier, or unary operator
Error (10500): VHDL syntax error at jkff.vhd(29) near text ’
Error (10500): VHDL syntax error at jkff.vhd(33) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at jkff.vhd(33) near text ‘
Error (10500): VHDL syntax error at jkff.vhd(33) near text ’
Info: Found 0 design units, including 0 entities, in source file jkff.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
Error: Peak virtual memory: 218 megabytes
Error: Processing ended: Sat Aug 04 08:08:34 2012
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 21 errors, 0 warnings