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VHDL: Testbench output off by 1 clock delay

Posted 02 September 2013 - 06:28 PM

Background: I'm trying to calculate two matrix multiplications. I have a file called DCT_beh that specifies the behavior of a chip that handles such a calculation. In the file I've managed to specify the following: the program waits until Start = 1 and then it reads in an array called Inblock. Inblock is then multiplied by a constant matrix, COSBLOCK, and then the result is outputted to another array called TEMPBLOCK. For the first step I'm just trying to get TEMPBLOCK to output correctly before I move onto the second matrix calculation. In my testbench file I feed in 64 values for Inblock using a loop. After running the simulation I notice that the first clock delay after Done = 0 is a value that I don't need/know where it comes from. The correct output matrix values are there but they are interrupted by a value that is not supposed to be a part of TEMPBLOCK.

Question: How can I correct my code so that the incorrect values are not longer showing up?

Attempt: I've tried outputting the Inblock and all values output correctly so the problem lies somewhere between TEMPBLOCK calculation and output loop. I've changed around the testbench code too but this problem still follows me. I have a feeling it may be related to the DCT_beh file since that is where the hardcoding takes place after Done = 0.

Files:

DCT_BEH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
entity DCT_beh is
        port (
                Clk :           in std_logic;
                Start :         in std_logic;
                Din :           in INTEGER := 0;
                Done :          out std_logic;
                Dout :          out INTEGER := 0
              );
end DCT_beh;

architecture behavioral of DCT_beh is
begin
        process
                type RF is array ( 0 to 7, 0 to 7 ) of INTEGER;
                --------------------------------------------------
                --you may modify below variables or declare new ones  
                --for the behavioral model
                --------------------------------------------------				
                variable i, j, k        : INTEGER;
                variable InBlock        : RF;
                variable COSBlock       : RF;
                variable TempBlock      : RF;
                variable OutBlock       : RF;
                variable A, B, P, Sum   : INTEGER; 
				
        begin
                -------------------------------
                -- Initialize parameter matrix
                -------------------------------
                COSBlock := ( 
        ( 125,  122,    115,    103,    88,     69,     47,     24  ),
        ( 125,  103,    47,     -24,    -88,    -122,   -115,   -69  ),
        ( 125,  69,     -47,    -122,   -88,    24,     115,    103  ),
        ( 125,  24,     -115,   -69,    88,     103,    -47,    -122  ),
        ( 125,  -24,    -115,   69,     88,     -103,   -47,    122  ),
        ( 125,  -69,    -47,    122,    -88,    -24,    115,    -103  ),
        ( 125,  -103,   47,     24,     -88,    122,    -115,   69  ),
        ( 125,  -122,   115,    -103,   88,     -69,    47,     -24  )
                        );

	--Starting
	 wait until Start = '1';
	 
	 done <= '0';
	 
	--Read Input Data
		for i in 0 to 7 loop
			for j in 0 to 7 loop	
				wait until Clk = '1' and clk'event;
				InBlock(i,j) := Din;
			end loop;
		end loop;
		
	--TempBlock = COSBLOCK * InBlock 
	  
		for i in 0 to 7 loop
			for j in 0 to 7 loop
				Sum := 0;
				--tempblock(i,j) := 0;
				for k in 0 to 7 loop
				
					A := COSBlock( i, k ); 
					B := InBlock( k, j ); 
					P := A * B; 
					Sum := Sum + P; 
					if( k = 7 ) then 
					TempBlock(i,j) := Sum;
					end if;		
					--TempBlock(i,j):= TempBlock(i,j) + (COSBlock(i,k) *InBlock(k,j));
				end loop;
			end loop;
		end loop;

		
	
		--OutBlock = TempBlock * COS1
		for i in 0 to 7 loop
			for j in 0 to 7 loop
				Sum := 0;
				--outblock(i,j) := 0;
				for k in 0 to 7 loop
					A:= TempBlock(i,k);
					B:= COSBlock(j,k);
					P := A * B;
					Sum := Sum + P;
					if( k = 7 ) then 
					OutBlock( i, j ) := Sum;
					end if;
					--OutBlock(i,j):= OutBlock(i,j) + TempBlock(i,k)*COSBlock(j,k);
				end loop;
			end loop;
		end loop;
		
	--Finishing 
		--dout <= 0;
		
		wait until Clk = '1' and Clk'event;
		Done <= '1';
		
		--Output Data
		for i in 0 to 7 loop
			for j in 0 to 7 loop
				wait until Clk = '1' and clk'event;
				Done <= '0';
				Dout <=  tempblock(i,j);
			end loop;
		end loop;
	end process; 	  
end behavioral;


Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
 
ENTITY lab4b_tb IS
END lab4b_tb;
 
ARCHITECTURE behavior OF lab4b_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DCT_beh
    PORT(
         Clk : IN  std_logic;
         Start : IN  std_logic;
         Din : IN  INTEGER;
         Done : OUT  std_logic;
         Dout : OUT  INTEGER
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Start : std_logic := '0';
   signal Din : INTEGER := 0;

 	--Outputs
   signal Done : std_logic;
   signal Dout : INTEGER := 0;
	
   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DCT_beh PORT MAP (
          Clk => Clk,
          Start => Start,
          Din => Din,
          Done => Done,
          Dout => Dout
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
	
	variable i, j : INTEGER;
	variable cnt : INTEGER;
	
   begin
		
		--		din<=0;
           
			--din <= 255;
			
		for i in 0 to 63 loop
            wait until clk = '1' and clk'event;
            if i = 0 then
                Start <= '1','0' after clk_period;
				end if;
				--din <= i;
				if (i < 24) then
					din <= 255;
				elsif (i > 40) then
					din <= 255;
				else
					din <= 0;
				end if;
		end loop;
		
		din <= 0;
		wait;
	
		end process;

END;


Simulation picture attached.

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