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#1 cobb878   User is offline

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VHDL or verilog SR latch

Posted 27 November 2013 - 09:29 PM

I'm trying to program my NEXYS2 board with a SR latch with NAND gates with an enable signal C. My inputs are (S, R, C) and outputs are (Q, Qbar). below is some code in VHDL that I tried but keep getting errors about my clock except I'm not using a clock I'm doing this asynchronously. if you know it in verilog that's okay too. Thank you in advance

    if (C = '1') then
        Q <= (R nand Qbar);
        Qbar <= (S nand Q);
    end if;
end process;

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