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#1 Heathersmithx   User is offline

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Computer Architecture: Set Associative Cache Addressing

Posted 28 April 2019 - 12:26 AM

I'm struggling with this whole set associative cache addressing thing. Just pretty much everything. Can anyone explain this simply to me. I've been reading and watching videos about it all day. Here is the question I'm sort of struggling with, so you have an idea of what I'm trying to do. If you can help me with even one of the addresses I can figure everything else out. I just have no idea how to answer this. What is the address supposed to look like exactly?

.5.7.1 [10] <5.4> Using the sequence of references from Exercise 5.2, show the fi nal cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block off set bits, and if it is a hit or a miss.

Exercise 5.2 (3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253)

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