[ShotokanDeity]

Hi everyone,

I am currently in a Computer Organization course and we have been discussing flip-flops for the past week. However, I still don't understand them. I'm not sure how to follow the flow of logic or how to use them to implement a sequential counter. More specifically, a Gray Counter using Digital Works. I am trying to create a JK flip-flop to sequentially change the bit sequence like this: 000 - 001 - 011 - 010 - 110 - 111 - 101 - 100. It is clocked, and uses only one other input. The input (0 or 1) determines whether the counter counts up (in the order I typed the bit sequence) or down (reverse).

It doesn't have to be a JK FF, it can be a T or D FF as well. Anyway, if anyone can help me out with understanding flip-flops and how to create a sequential logic circuit I will greatly appreciate it.


Thanks,
Shoto

[PennyBoki]

Well I'll try to explain, I hope you can understand me.

I see from the number of bits you are going to need three flip-flops. I recommend using D flip-fops because the table is easier to remeber

Q | Q+ | D
__________
0 | 0 | 0
0 | 1 | 1
1 | 0 | 0
1 | 1 | 1


So making the table is easy

Q1 | Q2 | Q3 || Q1+ | Q2+ Q3+ || D1 | D2 | D3
___________________________________________
0 | 0 | 0 || 0 | 0 | 1 || 0 | 0 | 1
0 | 0 | 1 || 0 | 1 | 1 || 0 | 1 | 1
0 | 1 | 0 || 1 | 1 | 0 || 1 | 1 | 0
0 | 1 | 1 || 0 | 1 | 0 || 0 | 1 | 0
1 | 0 | 0 || 0 | 0 | 0 || 0 | 0 | 0
1 | 0 | 1 || 1 | 0 | 0 || 1 | 0 | 0
1 | 1 | 0 || 1 | 1 | 1 || 1 | 1 | 1
1 | 1 | 1 || 1 | 0 | 1 || 1 | 0 | 1

After you make the truth tables where you should make the formula for D1, D2, D3 all you have to do is connect them.

As for the input:


I'm assuming that this is asynchronized or NOTsynchronized sequential counter. So that means that the clock of the second and third FF will depend upon the value of INPUT and the VALUE of the Q and NOT(Q) of the previous FF.

So in the first FF you just assign CLK(clock), to the second you'll need a circuit like this

C2 = (Q1) AND (INPUT) OR (NOT(Q1)) AND (NOT(INPUT))

C3= (Q2) AND (INPUT) OR (NOT(Q2)) AND (NOT(INPUT))

Hope this helps.

This post has been edited by PennyBoki: 05 February 2008 - 07:24 PM

[ShotokanDeity]

Thanks Penny!

OK so I did actually create a truth/excitation table for the D FFs and created a circuit that works. Your explanation did help. So I understand the "big picture" operation of FFs, but what I still don't understand is the literal flow of logic within the FF itself.

I'll attach some examples of what I don't understand when I'm back on my own laptop.

[ShotokanDeity]

OK so I know it's been awhile, but my comp. decided to go stupid on me. Anyway, I have attached a .zip file that contains a .pdf/powerpoint presentation. The part I'm not understanding is the actual flow of logic within the FF's themselves. One part that confuses me is how the OR gates use inputs that sepend on the outputs. So how is the gate activated at all? It initially only has 1 input, right?

An example of my question is on slide 5. Throughout the rest of the slides there are multiple other examples, including much more complicated FF's. I understand what FF's do, but I don't understand how they do it, what the literal flow of logic is.

It's not at all integral for my course, but I would like to know for myself.

Thanks for helping!


EDIT: forgot to attach the file

Attached File(s)

•  CDA3103Chapter3Part1.zip (444.85K)
  Number of downloads: 730

This post has been edited by ShotokanDeity: 12 February 2008 - 12:34 PM

[Louisda16th]

Lets look at two not gates set up like this (called a NOT latch):



Lets assume that the Gate with input A is 1. Forget the other one for now. Suppose A = 1, then the output of the top gate is 0 ("NOT A"). This serves as an input for the second gate. Since the input to this gate is a zero, its output will be 1. The two outputs, as you can see are complements of each other. We don't have to worry about a situation where both gates are given the same input at the same time - its almost impossible for the gate delays to be exactly the same. In the extremely rare case that this should happen, a tiny disturbance in the circuit will stabilize it.
Now the NOT latch as such isn't very useful. Lets add an AND gate before the inputs to each NOT gate like so:



Which is a NAND Latch.

http://tbn0.google.com/images?q=tbn:NO-Jrux2UxMDJM:http://www.play-hookey.com/digital/images/rs-110.gif

Lets look at the four input combinations:

AB Q Q'
00 * *
01 1 0
10 0 1
11 Q Q'

Forget the first one for now. In the second combination, A = 0 and B = 1. If you look at the truth table of a NAND gate, its output is always 1 if at least one of its inputs is 0. Therefore, irrespective of the second input at "Gate A", its output will be 1. Hence Q is 1. Now look at the inputs to "Gate B". Both are 1 and hence its output will be a zero. This shows Q' = 0.
We could have started with gate B as well. Since B = 1, Gate B's output is unpredictable if we do not know ehat its second input will be. However, since A is 0, the output of Gate A will always be 1, giving and input of 11 to Gate B.

Combination 3 can be explained similarly.

In combination 4, since both gates are fed with an input of 1, they're outputs will depend on what they're second inputs are. Assume that the latch was SET before we applied the input. The inputs to the top gate (Gate A) are 1 and 1. Hence its output will be unchanged at 0. The same holds for gate B. The inputs to B are 1 and 0. Hence its output is 1.
The same logic applies when the latch is initially RESET.

Now for combination 1 - the one to be avoided. If A = 0 and supposed its second input is 0, Gate A will give an output of 1. Now since the inputs to gate B are 1 and zero, its output is also a one. Now we don't want a latch where both its outputs are the same.

As a convention, the A input is denoted by S' since it resets the latch when it is set to 0. B is denoted by R since it sets the latch. The inputs are active low in this case.

Hope this explained how latches work .

A flip-flop is technically, a clocked latch i.e. a latch with a clocked input, you use a NAND gate for this purpose:

The NAND gates allows your Inputs to "reach" the NAND Latch only when the enable or clock input is held at 1.

Hope this helps

This post has been edited by Louisda16th: 13 February 2008 - 06:13 AM

[ShotokanDeity]

Thanks Louis! Yes that did help. I always tried to reason that a gate could not function until it had both inputs, but since the inputs were dependent on the other gates output technically the circuit shouldn't even work. Your explanation cleared that misconception up though.

You just explained that much better than both the text and the teacher!

[Louisda16th]

ShotokanDeity, on 14 Feb, 2008 - 11:01 PM, said:

Thanks Louis!

You're welcome anytime!

Quote

You just explained that much better than both the text and the teacher!

Thank You

[Nayana]

I agree. That was a very good explanation.

[Louisda16th]

I was wondering. Is digital logic design a course computer science students have problems with?

[ShotokanDeity]

So far it just seems to depend on how much you study and how well the professor can actually teach the subject matter. Often times the professor knows the material so well that he forgets we are learning this for the first time, and he can't communicate the idea in a simple enough manner for the majority of the class (including me!).

So from my limited experience with my one class/professor, it seems a little on the difficult side. The most difficult class I've taken, to be honest.



edit: fixed grammatical errors.

This post has been edited by ShotokanDeity: 16 February 2008 - 08:39 AM

[Louisda16th]

Mmm. I think I could manage a set of tutorials on the subject if there's popular demand.

[ShotokanDeity]

I would read 'em all. And I would tell all my classmates to come read them as well!

[Nayana]

For me, digital logic is one of the easiest parts of programming. But this is probably due to me taking Linguistics as my first major, and in that we had to do discrete mathematics. By the time I got onto programming, digital logic was like a native language to me.